As the speed of an electronic circuit increases, there is a strong demand for generating a timing signal with high resolution and high accuracy. FIG. 6 shows a conventional structure of a timing signal generation circuit utilizing a synchronous down counter 10. In this example, delay data is set to the synchronous down counter 10 by a LOAD signal, and the delay data is synchronously down counted by a clock (CLK) signal. When the down counter 10 reaches "0", an All-Zero signal is generated at its output, which is a timing signal showing the delay time of an integer multiple of the clock signal period.
In this conventional example, an accurate timing signal is obtained by utilizing a clock signal which is generated by utilizing a crystal oscillator with high stability. However, since there is a limit in the speed of the synchronous down counter 10, it is not practically possible to generate a higher resolution signal, such as a timing signal having a repetition rate of 10 nanosecond or less by using a clock signal period of 10 nanosecond or less.
FIG. 7 shows an another example of conventional circuit diagram that generates a timing signal having a smaller delay time than a clock signal period. In this example, the output of the synchronous down counter 10 is connected to input terminals A of a series of selectors 21-23. The other input terminals B of the selectors 21-23 are connected to the output of the counter 10 through buffers 31.sub.1 -31.sub.7 in a manner shown in FIG. 7.
More precisely, the input terminal A of the selector 21 is directly provided with the output of the counter 10 while the input terminal B is provided with the output of the counter 10 though the buffer 31.sub.1. The input terminal A of the selector 22 is directly provided with the output of the selector 21 while the input terminal B is provided with the output of the selector 21 through the buffer 31.sub.2 and 31.sub.3. Similarly, the input terminal A of the selector 23 is directly provided with the output of the selector 22 while the input terminal B is provided with the output of the selector 22 through the buffers 31.sub.4 -31.sub.7. Each of the buffers 31.sub.1 -31.sub.7 has a delay time which is smaller than the clock signal period. The delay data is supplied to the synchronous down counter 10 and the selectors 21-23, respectively. The output of the last stage selector, in this example, the selector 23 is used as a timing signal.
In this arrangement, an All-Zero signal which is an output signal from the down counter 10 is input to the input terminal A of the selector 21, and at the same time to the input terminal B via the buffer 31.sub.1. By selecting either the terminal A or the terminal B of the selector 21 by the delay data, timing signals having a timing difference of a propagation delay time of the buffer 31.sub.1 can be generated at an output terminal Y.
An output signal from the selector 21 is input to the terminal A of the selector 22, and at the same time to the terminal B via two stages of the buffers 31.sub.2 and 31.sub.3. By selecting either the terminal A or the terminal B of the selector 22 by the delay data, timing signals having a timing difference of a sum of delay times of the buffers 312 and 313 can be generated at an output terminal Y.
Similarly, an output signal of the selector 22 is provided to the input terminal A of the selector 23, and at the same time to the terminal B terminal of the selector 23 via four stages of buffers 31.sub.4 -31.sub.7. By selecting either the terminal A or the terminal B of the selector 23 by the delay data, timing signals having a timing difference of a sum of delay times of the buffers 31.sub.4 -31.sub.7.
The more increased number of delay times are available by further connecting and selecting buffers, for example, eight stages of buffers or sixteen stages of buffers in a manner described above. Therefore, a timing signal can be generated wherein each delay time step is a portion of a clock signal period.
In this conventional method, since the unit of delay time is set to a propagation time delay Tpd of each buffer 31, there are some drawbacks. Namely, a timing signal error will be incorporated because of the changes in the propagation time delay Tpd of the buffers 31 caused by a change in a power supply voltage of the buffers 31 or a change in temperature surrounding the buffers 31.
Further, a timing signal error will be incorporated because of the discrepancy of propagation delay times between the semiconductor ICs caused by the discrepancy of the IC production process. Furthermore, delay data set to a synchronous down counter 10 changes the number of signals or the number of signals passing through the buffers 31, which will change the self-generated heat of the buffers 31. An error of a timing signal will be further generated by the temperature change caused by this self-generated heat. This drawback is especially prominent in COOS circuit wherein the difference in the consumption of electric power between at rest and in operation is large.
The change in the propagation time delay Tpd stated above causes discontinuous points at every clock signal period, as shown in FIG. 8. For example, in case where the clock signal CLK is divided by m buffers 31 as shown in FIG. 8, and if the propagation time delay Tpd is larger than the value of 1/m of the clock signal period, discontinuous points are incorporated in the timing signal as shown at the solid line in FIG. 8. Further, when the propagation time delay Tpd is smaller than 1/m of the clock signal period, discontinuous points are incorporated as shown at the dotted line of FIG. 8.
Aside from the delay time caused by the buffers 31, there is also a delay time involved in a timing signal caused by the plurality of selectors. Although this delay in the selectors will not directly affect the variable delay times in the buffers 31, it affects the timing signal since the selectors are connected in series in the timing signal path, and thus causes additional timing errors in the timing signal by the same reasons described above.
As in the foregoing, in the conventional method of setting delay data for generating a timing signal having an increment of delay time which is smaller than a clock signal cycle, the accuracy of such timing signal is limited. This is because the timing signal inevitably includes errors caused by the changes of temperature and power supply voltage in the IC which incorporates timing signal generation circuit, non-uniformity in the IC characteristics, the temperature changes caused by the changes in the self-generated heat of the buffers, and the time delay and the change thereof caused in a plurality of selector circuits. Thus, it is not possible to generate a high resolution and accuracy timing signal in the conventional method.